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INTEGRATED CIRCUITS
DATA SHEET
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* The IC06 74HC/HCT/HCU/HCMOS Logic Family Specifications
74HC/HCT4066 Quad bilateral switches
Product specification Supersedes data of 1998 Oct 02 File under Integrated Circuits, IC06 1998 Nov 10
Philips Semiconductors
Product specification
Quad bilateral switches
FEATURES * Very low "ON" resistance: 50 (typ.) at VCC = 4.5 V 45 (typ.) at VCC = 6.0 V 35 (typ.) at VCC = 9.0 V * Output capability: non-standard * ICC category: SSI. GENERAL DESCRIPTION The 74HC/HCT4066 are high-speed Si-gate CMOS devices and are pin compatible with the "4066" of the "4000B" series. They are specified in compliance with JEDEC standard no. 7A. QUICK REFERENCE DATA GND = 0 V; Tamb = 25 C; tr = tf = 6 ns
74HC/HCT4066
The 74HC/HCT4066 have four independent analog switches. Each switch has two input/output terminals (nY, nZ) and an active HIGH enable input (nE). When nE is LOW the belonging analog switch is turned off. The "4066" is pin compatible with the "4016" but exhibits a much lower "ON" resistance. In addition, the "ON" resistance is relatively constant over the full input signal range.
TYPICAL SYMBOL tPZH/ tPZL tPHZ/ tPLZ CI CPD CS Notes 1. CPD is used to determine the dynamic power dissipation (PD in W): a) PD = CPD x VCC2 x fi + {(CL + CS) x VCC2 x fo} where: b) fi = input frequency in MHz c) fo = output frequency in MHz d) {(CL + CS) x VCC2 x fo} = sum of outputs e) CL = output load capacitance in pF f) CS = maximum switch capacitance in pF g) VCC = supply voltage in V 2. For HC the condition is VI = GND to VCC For HCT the condition is VI = GND to VCC - 1.5 V PARAMETER turn-on time nE to Vos turn-off time nE to Vos input capacitance power dissipation capacitance per switch max. switch capacitance notes 1 and 2 CONDITIONS HC CL = 15 pF; RL = 1 k; VCC = 5 V 11 13 3.5 11 8 HCT 12 16 3.5 12 8 ns ns pF pF pF UNIT
1998 Nov 10
2
Philips Semiconductors
Product specification
Quad bilateral switches
ORDERING INFORMATION TYPE NUMBER 74HC4066 74HC4066 74HC4066 74HC4066 74HCT4066 74HCT4066 74HCT4066 74HCT4066 PACKAGE NAME DIP14 SO14 SSOP14 TSSOP14 DIP14 SO14 SSOP14 TSSOP14 DESCRIPTION plastic dual in-line package; 14 leads (300 mil) plastic small outline package; 14 leads; body width 3.9 mm
74HC/HCT4066
VERSION SOT27-1 SOT108-1 SOT337-1 SOT27-1 SOT108-1 SOT337-1
plastic shrink small outline package; 14 leads; body width 5.3 mm plastic dual in-line package; 14 leads (300 mil) plastic small outline package; 14 leads; body width 3.9 mm plastic shrink small outline package; 14 leads; body width 5.3 mm
plastic thin shrink small outline package; 14 leads; body width 4.4 mm SOT402-1
plastic thin shrink small outline package; 14 leads; body width 4.4 mm SOT402-1
PIN DESCRIPTION PIN NO. 1, 4, 8, 11 2, 3, 9, 10 7 13, 5, 6, 12 14 SYMBOL 1Y to 4Y 1Z to 4Z GND 1E to 4E VCC independent inputs/outputs independent inputs/outputs ground (0 V) enable inputs (active HIGH) positive supply voltage NAME AND FUNCTION
handbook, halfpage
handbook, halfpage
1Y 1Z 2Z 2Y 2E 3E GND
1 2 3 4 5 6 7
MGR253
14 VCC 13 1E 12 4E
1Y 13 1E 1Z 2Y 2Z 3Y 3Z 4Y 4Z
MGR254
1 2 4 3 8 9 11 10
5
2E
4066
11 4Y 10 4Z 9 3Z 6 3E
12
4E
8 3Y
Fig.1 Pin configuration.
Fig.2 Logic symbol.
1998 Nov 10
3
Philips Semiconductors
Product specification
Quad bilateral switches
74HC/HCT4066
handbook, halfpage
1 13 # 4 5# 8 6# 11 12 #
2
handbook, halfpage
1 13 #
1 X1
1
2
3
4 5#
1 X1
1
3
9 8 10 6#
1 X1
1
9
11
MGR255
1 X1
1
10
12 #
MGR256
a.
b.
Fig.3 IEC logic symbol.
FUNCTION TABLE INPUT NE L H Note 1. H = HIGH voltage level; L = LOW voltage level.
13 handbook, halfpage 1E 1 1Y 5 2E 4 2Y 6 3E 8 3Y 12 4E 11 4Y
handbook, halfpage
SWITCH off on
nY
1Z 2
2Z 3
3Z 9
4Z 10
MGR257
nE
VCC
VCC
GND
nZ
MGR258
Fig.4 Functional diagram.
Fig.5 Schematic diagram (one switch).
1998 Nov 10
4
Philips Semiconductors
Product specification
Quad bilateral switches
74HC/HCT4066
RATINGS Limiting values in accordance with the Absolute Maximum System (IEC 134) Voltages are referenced to GND (GND = 0 V) SYMBOL VCC IIK ISK IIS ICC; IGND Tstg Ptot PARAMETER DC supply voltage DC digital input diode current DC switch diode current DC switch current DC VCC or GND current storage temperature range power dissipation per package plastic DIL plastic mini-pack (SO) PS Note 1. To avoid drawing VCC current out of terminal nZ, when switch current flows in terminal nY, the voltage drop across the bidirectional switch must not exceed 0.4 V. If the switch current flows into terminal nZ, no VCC current will flow out of terminal nY. In this case there is no limit for the voltage drop across the switch, but the voltages at nY and nZ may not exceed VCC or GND. RECOMMENDED OPERATING CONDITIONS 74HC SYMBOL VCC VI VS Tamb Tamb tr, tf PARAMETER min. DC supply voltage DC input voltage range DC switch voltage range operating ambient temperature range operating ambient temperature range input rise and fall times 2.0 GND GND -40 -40 6.0 typ. 5.0 max. 10.0 VCC VCC +85 +125 1000 500 400 250 min. 4.5 GND GND -40 -40 6.0 typ. 5.0 max. 5.5 VCC VCC +85 +125 500 V V V C C ns VCC = 2.0 V VCC = 4.5 V VCC = 6.0 V VCC = 10.0 V see DC and AC CHARACTERISTICS 74HCT UNIT CONDITIONS power dissipation per switch 750 500 100 mW mW mW -65 MIN. -0.5 MAX. +11.0 20 20 25 50 +150 UNIT V mA mA mA mA C for temperature range: -40 to +125 C 74HC/HCT above +70 C: derate linearly with 12 mW/K above +70 C: derate linearly with 8 mW/K for VI < - 0.5 V or VI > VCC + 0.5 V for VS < - 0.5 V or VS > VCC + 0.5 V for -0.5 V < VS < VCC + 0.5 V CONDITIONS
1998 Nov 10
5
Philips Semiconductors
Product specification
Quad bilateral switches
DC CHARACTERISTICS FOR 74HC/HCT For 74HC: VCC = 2.0, 4.5, 6.0 and 9.0 V; For 74HCT: VCC = 4.5 V Tamb (C) 74HC/HCT SYMBOL PARAMETER +25 - 54 42 32 RON ON-resistance (rail) 80 35 27 20 RON ON-resistance (rail) 42 35 27 RON maximum variation of ON-resistance between any two channels - 5 4 3 Note - 95 84 70 - 75 65 55 80 75 60 -40 to +85 - 118 105 88 - 95 82 70 - 106 94 78 -40 to +125 - 142 126 105 - 115 100 85 - 128 113 95
74HC/HCT4066
TEST CONDITIONS UNIT V IS CC (V) (A) 2.0 4.5 6.0 9.0 2.0 4.5 6.0 9.0 2.0 4.5 6.0 9.0 2.0 4.5 6.0 9.0 100
VIS
VI
min. typ. max. min. max. min. max. RON ON-resistance (peak) VCC VIH to or 1000 GND VIL 1000 1000 100 GND VIH or 1000 VIL 1000 1000 100 1000 1000 1000 VCC VIH to or GND VIL VCC VIH or VIL
100 -
1. At supply voltages approaching 2 V, the analog switch ON-resistance becomes extremely non-linear. Therefore it is recommended that these devices be used to transmit digital signals only, when using these supply voltages.
1998 Nov 10
6
Philips Semiconductors
Product specification
Quad bilateral switches
74HC/HCT4066
dbook, full pagewidth
HIGH (from enable inputs) nY
V nZ Iis GND
MGR259
Vis = 0 to VCC - GND
Fig.6 Test circuit for measuring ON-resistance (RON).
handbook, full pagewidth
LOW (from enable inputs) nY VI = VCC or GND A nZ A
VO = GND or VCC
GND
MGR260
Fig.7 Test circuit for measuring OFF-state current.
handbook, full pagewidth
HIGH (from enable inputs) nY VI = VCC or GND A nZ A
VO (open circuit)
GND
MGR261
Fig.8 Test circuit for measuring ON-state current.
1998 Nov 10
7
Philips Semiconductors
Product specification
Quad bilateral switches
74HC/HCT4066
handbook, halfpage
60
MGR262
RON ()
VCC = 4.5 V
50 6V 40 9V
30
20
10 0 1.8 3.6 5.4 7.2 Vis (V) 9
Fig.9 Typical ON-resistance (RON) as a function of input voltage (Vis) for Vis = 0 to VCC.
1998 Nov 10
8
Philips Semiconductors
Product specification
Quad bilateral switches
DC CHARACTERISTICS FOR 74HC Voltage are referenced to GND (ground = 0 V) Tamb (C) 74HC SYMBOL PARAMETER +25 min. typ. max. VIH HIGH-level input voltage 1.5 3.15 4.2 6.3 VIL LOW-level input voltage 1.2 2.4 3.2 4.7 0.8 2.1 2.8 4.3 II input leakage current analog switch OFF-state current per channel analog switch ON-state current quiescent supply current 0.50 1.35 1.80 2.70 0.1 0.2 0.1 -40 to +85 min. 1.5 3.15 4.2 6.3 0.50 1.35 1.80 2.70 1.0 2.0 1.0 -40 to +125 UNIT V CC (V)
74HC/HCT4066
TEST CONDITIONS
VI
OTHER
max. min. max 1.5 3.15 4.2 6.3 0.50 1.35 1.80 2.70 1.0 2.0 1.0 A A V V 2.0 4.5 6.0 9.0 2.0 4.5 6.0 9.0 6.0 VCC 10.0 or GND VS = VCC - GND (see Fig.7)
IS
10.0 VIH or VIL 10.0 VIH or VIL 6.0
IS
0.1
1.0
1.0
A
VS = VCC - GND (see Fig.8)
ICC
2.0 4.0
20.0 40.0
40.0 80.0
A
VCC Vis = GND or VCC; 10.0 or GND Vos = VCC or GND
1998 Nov 10
9
Philips Semiconductors
Product specification
Quad bilateral switches
AC CHARACTERISTICS FOR 74HC GND = 0 V; tr = tf = 6 ns; CL = 50 pF Tamb (C) 74HC SYMBOL PARAMETER +25 min. tPHL/tPLH propagation delay Vis to Vos typ. 8 3 2 2 tPZH/tPZL turn-on time nE to Vos 36 13 10 8 tPHZ/tPLZ turn-off time nE to Vos 44 16 13 16 max. 60 12 10 8 100 20 17 13 150 30 26 24 -40 to +85 min. max. 75 15 13 10 125 25 21 16 190 38 33 16 -40 to +125 min. max. 90 18 15 12 150 30 26 20 225 45 38 20 ns ns ns
74HC/HCT4066
TEST CONDITIONS UNIT V CC (V) 2.0 4.5 6.0 9.0 2.0 4.5 6.0 9.0 2.0 4.5 6.0 9.0 RL = 1 k; CL = 50 pF (see Figs 19 and 20) RL = 1 k; CL = 50 pF (see Figs 19 and 20) OTHER
RL = ; CL = 50 pF (see Fig.18)
1998 Nov 10
10
Philips Semiconductors
Product specification
Quad bilateral switches
DC CHARACTERISTICS FOR 74HCT Voltages are referenced to GND (ground = 0 V) Tamb (C) 74HCT SYMBOL PARAMETER +25 min. VIH HIGH-level input voltage LOW-level input voltage input leakage current analog switch OFF-state current per channel analog switch ON-state current quiescent supply current additional quiescent supply current per input pin for unit load coefficient is 1 (note 1) 100 2.0 typ. 1.6 -40 to +85 max. min. max. 2.0 -40 to +125 min. 2.0 max. V 4.5 to 5.5 4.5 to 5.5 5.5 UNIT V CC (V)
74HC/HCT4066
TEST CONDITIONS
VI
OTHER
VIL
1.2
0.8
0.8
0.8
V
II
0.1
1.0
1.0
A
VCC or GND VIH or VIL VIH or VIL VCC or GND VS = VCC - GND (see Fig.7)
IS
0.1
1.0
1.0
A
5.5
IS
0.1
1.0
1.0
A
5.5
VS = VCC - GND (see Fig.8) Vis = GND or VCC; Vos = VCC or GND
ICC
2.0
20.0
40.0
A
4.5 to 5.5 4.5 to 5.5
ICC
360
450
490
A
VCC - other inputs at 2.1 V VCC or GND
Note 1. The value of additional quiescent supply current (ICC) for a unit load of 1 is given here. To determine ICC per input, multiply this value by the unit load coefficient shown in the table below. Table 1 INPUT nE UNIT LOAD COEFFICIENT 1.00
1998 Nov 10
11
Philips Semiconductors
Product specification
Quad bilateral switches
AC CHARACTERISTICS FOR 74HCT GND = 0 V; tr = tf = 6 ns Tamb (C) 74HCT SYMBOL PARAMETER +25 -40 to +85 -40 to +125 min. max. 18 36 53 ns ns ns 4.5 4.5 4.5
74HC/HCT4066
TEST CONDITIONS UNIT V CC (V) OTHER
min. typ. max. min. max. tPHL/tPLH tPZH/tPZL tPHZ/tPLZ propagation delay Vis to Vos turn-on time nE to Vos turn-off time nE to Vos 3 12 20 12 24 35 15 30 44
RL = ; CL = 50 pF (see Fig.18) RL = 1 k; CL = 50 pF (see Figs 19 and 20) RL = 1 k; CL = 50 pF (see Figs 19 and 20)
ADDITIONAL AC CHARACTERISTICS FOR 74HC/HCT Recommended conditions and typical values GND = 0 V; tr = tf = 6 ns SYMBOL PARAMETER sine wave distortion f = 1 kHz sine wave distortion f = 10 kHz switch "OFF" signal feed-through crosstalk between any two switches V(p-p) crosstalk voltage between enable or address input to any switch (peak-to-peak value) minimum frequency response (-3 dB) maximum switch capacitance TYP. 0.04 0.02 0.12 0.06 -50 -50 -60 -60 110 220 UNIT % % % % dB dB dB dB mV mV VCC (V) 4.5 9.0 4.5 9.0 4.5 9.0 4.5 9.0 4.5 9.0 note 3 VIS(p-p) (V) 4.0 8.0 4.0 8.0 note 3 CONDITIONS RL = 10 k; CL = 50 pF (see Fig.16) RL = 10 k; CL = 50 pF (see Fig.16) RL = 600 ; CL = 50 pF; f = 1 MHz (see Figs 10 and 17) RL = 600 ; CL = 50 pF; f = 1 MHz (see Fig.12) RL = 600 ; CL = 50 pF; f = 1 MHz (nE, square wave between VCC and GND, tr = tf = 6 ns) (see Fig.14) note 4 RL = 50 ; CL = 10 pF (see Figs 11 and 15)
fmax CS Notes
180 200 8
MHz MHz pF
4.5 9.0
1. Vis is the input voltage at nY or nZ terminal, whichever is assigned as an input. 2. Vos is the output voltage at nY or nZ terminal, whichever is assigned as an output. 3. Adjust input voltage Vis is 0 dBM level (0 dBM = 1 mW into 600 ). 4. Adjust input voltage Vis is 0 dBM level at Vos for 1 MHz (0 dBM = 1 mW into 50 ).
1998 Nov 10
12
Philips Semiconductors
Product specification
Quad bilateral switches
74HC/HCT4066
MGR263
handbook, full pagewidth
0
(dB) -20
-40
-60
-80
-100 10
102
103
104
105
f (kHz)
106
Test conditions: VCC = 4.5 V; GND = 0 V; RL = 50 ; Rsource = 1 k.
Fig.10 Typical switch "OFF" signal feed-through as a function of frequency.
MGR264
handbook, full pagewidth
5
(dB)
0
-5 10
102
103
104
105
f (kHz)
106
Test conditions: VCC = 4.5 V; GND = 0 V; RL = 50 ; Rsource = 1 k.
Fig.11 Typical frequency response.
1998 Nov 10
13
Philips Semiconductors
Product specification
Quad bilateral switches
74HC/HCT4066
handbook, full pagewidth
VCC 2RL nY/nZ RL 2RL channel ON
MGM265
0.1 F Vi
nZ/nY CL GND
Fig.12 Test circuit for measuring crosstalk between any two switches; channel ON condition.
handbook, full pagewidth
VCC 2RL nY/nZ
VCC 2RL nZ/nY Vos
2RL
channel OFF
2RL
CL dB GND
MGR266
Fig.13 Test circuit for measuring crosstalk between any two switches; channel OFF condition.
handbook, full pagewidth The crosstalk is defined as follows (oscilloscope output):
VCC 2RL
nE
VCC VCC GND 2RL nZ/nY 2RL CL Vos
fpage
nY/nZ V(p-p) 2RL
MGR267
D.U.T.
oscilloscope GND
MGR268
Fig.14 Test circuit for measuring crosstalk between control and any switch.
1998 Nov 10
14
Philips Semiconductors
Product specification
Quad bilateral switches
74HC/HCT4066
handbook, full pagewidth
VCC 2RL nY/nZ 2RL channel ON
MGR269
0.1 F sine-wave Vis
nZ/nY CL dB
Vos
GND
Adjust input voltage to obtain 0 dBM at Vos when fin = 1 MHz. After set-up frequency of fin is increased to obtain a reading of -3 dB at Vos.
Fig.15 Test circuit for measuring minimum frequency response.
handbook, full pagewidth
VCC 2RL nY/nZ nZ/nY DISTORTION METER GND
MGR270
10 F fin = 1 kHz Vis sine-wave
Vos
2RL channel ON
CL
Fig.16 Test circuit for measuring sine wave distortion.
handbook, full pagewidth
VCC 2RL nY/nZ 2RL channel OFF
MGR271
0.1 F Vis
nZ/nY CL dB
Vos
GND
Fig.17 Test circuit for measuring switch "OFF" signal feed-through.
1998 Nov 10
15
Philips Semiconductors
Product specification
Quad bilateral switches
AC WAVEFORMS
handbook, full pagewidth
74HC/HCT4066
tr 90% Vis 10% 50%
tf VCC
GND
Vos
50%
tPLH (1) HC: VM = 50%; VI = GND to VCC; HCT: VM = 1.3 V; VI = GND to 3 V.
tPHL
MGR272
Fig.18 Waveforms showing the input (Vis) to output (Vos) propagation delays.
tf 90 % nE INPUT V M (1) 10 % t PLZ OUTPUT LOW - to - OFF OFF - to - LOW t PHZ OUTPUT HIGH - to - OFF OFF - to - HIGH outputs enabled 90 %
tr
t PZL
50 % 10 % t PZH 50 % outputs disabled outputs enabled
MGA846
Fig.19 Waveforms showing the turn-on and turn-off times.
TEST CIRCUIT AND WAVEFORMS
VCC Vis VI D.U.T. RT CL GND
MGR273
handbook, full pagewidth
VCC VO RL switch open
PULSE GENERATOR
Fig.20 Test circuit for measuring AC performance.
1998 Nov 10
16
Philips Semiconductors
Product specification
Quad bilateral switches
Table 2 Conditions TEST tPZH tPZL tPHZ tPLZ others Table 3 Definitions for Figs 20 and 21: DEFINITION SWITCH GND VCC GND VCC open
74HC/HCT4066
VIS VCC GND VCC GND pulse
SYMBOL CL RT tr
load capacitance including jig and probe capacitance (see AC CHARACTERISTICS for values) termination resistance should be equal to the output impedance ZO of the pulse generator tf = 6 ns, when measuring fmax, there is no constraint on tr, tf with 50% duty factor
handbook, full pagewidth
tW 90% NEGATIVE INPUT PULSE VM 10% tTHL (tf) tTLH (tr) POSITIVE INPUT PULSE 10% tW 90% VM 0V
MGR274
AMPLITUDE
0V tTLH (tr) tTHL (tf) AMPLITUDE
Fig.21 Input pulse definitions.
Table 4 tr; tf FAMILY 74HC 74HCT AMPLITUDE VCC 3.0 V VM 50% 1.3 V fmax; PULSE WIDTH < 2 ns < 2 ns OTHER 6 ns 6 ns
1998 Nov 10
17
Philips Semiconductors
Product specification
Quad bilateral switches
PACKAGE OUTLINES DIP14: plastic dual in-line package; 14 leads (300 mil)
74HC/HCT4066
SOT27-1
D seating plane
ME
A2
A
L
A1
c Z e b1 b 14 8 MH wM (e 1)
pin 1 index E
1
7
0
5 scale
10 mm
DIMENSIONS (inch dimensions are derived from the original mm dimensions) UNIT mm inches A max. 4.2 0.17 A1 min. 0.51 0.020 A2 max. 3.2 0.13 b 1.73 1.13 0.068 0.044 b1 0.53 0.38 0.021 0.015 c 0.36 0.23 0.014 0.009 D (1) 19.50 18.55 0.77 0.73 E (1) 6.48 6.20 0.26 0.24 e 2.54 0.10 e1 7.62 0.30 L 3.60 3.05 0.14 0.12 ME 8.25 7.80 0.32 0.31 MH 10.0 8.3 0.39 0.33 w 0.254 0.01 Z (1) max. 2.2 0.087
Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT27-1 REFERENCES IEC 050G04 JEDEC MO-001AA EIAJ EUROPEAN PROJECTION
ISSUE DATE 92-11-17 95-03-11
1998 Nov 10
18
Philips Semiconductors
Product specification
Quad bilateral switches
74HC/HCT4066
SO14: plastic small outline package; 14 leads; body width 3.9 mm
SOT108-1
D
E
A X
c y HE vMA
Z 14 8
Q A2 A1 pin 1 index Lp 1 e bp 7 wM L detail X (A 3) A
0
2.5 scale
5 mm
DIMENSIONS (inch dimensions are derived from the original mm dimensions) UNIT mm A max. 1.75 A1 0.25 0.10 A2 1.45 1.25 A3 0.25 0.01 bp 0.49 0.36 c 0.25 0.19 D (1) 8.75 8.55 E (1) 4.0 3.8 0.16 0.15 e 1.27 0.050 HE 6.2 5.8 L 1.05 Lp 1.0 0.4 Q 0.7 0.6 0.028 0.024 v 0.25 0.01 w 0.25 0.01 y 0.1 0.004 Z (1) 0.7 0.3 0.028 0.012
inches 0.069
0.010 0.057 0.004 0.049
0.019 0.0100 0.35 0.014 0.0075 0.34
0.244 0.039 0.041 0.228 0.016
8 0o
o
Note 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. OUTLINE VERSION SOT108-1 REFERENCES IEC 076E06S JEDEC MS-012AB EIAJ EUROPEAN PROJECTION
ISSUE DATE 95-01-23 97-05-22
1998 Nov 10
19
Philips Semiconductors
Product specification
Quad bilateral switches
74HC/HCT4066
SSOP14: plastic shrink small outline package; 14 leads; body width 5.3 mm
SOT337-1
D
E
A X
c y HE vM A
Z 14 8
Q A2 pin 1 index Lp L 1 bp 7 wM detail X A1 (A 3) A
e
0
2.5 scale
5 mm
DIMENSIONS (mm are the original dimensions) UNIT mm A max. 2.0 A1 0.21 0.05 A2 1.80 1.65 A3 0.25 bp 0.38 0.25 c 0.20 0.09 D (1) 6.4 6.0 E (1) 5.4 5.2 e 0.65 HE 7.9 7.6 L 1.25 Lp 1.03 0.63 Q 0.9 0.7 v 0.2 w 0.13 y 0.1 Z (1) 1.4 0.9 8 0o
o
Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT337-1 REFERENCES IEC JEDEC MO-150AB EIAJ EUROPEAN PROJECTION
ISSUE DATE 95-02-04 96-01-18
1998 Nov 10
20
Philips Semiconductors
Product specification
Quad bilateral switches
74HC/HCT4066
TSSOP14: plastic thin shrink small outline package; 14 leads; body width 4.4 mm
SOT402-1
D
E
A
X
c y HE vMA
Z
14
8
Q A2 pin 1 index A1 Lp L (A 3) A
1
e bp
7
wM detail X
0
2.5 scale
5 mm
DIMENSIONS (mm are the original dimensions) UNIT mm A max. 1.10 A1 0.15 0.05 A2 0.95 0.80 A3 0.25 bp 0.30 0.19 c 0.2 0.1 D (1) 5.1 4.9 E (2) 4.5 4.3 e 0.65 HE 6.6 6.2 L 1.0 Lp 0.75 0.50 Q 0.4 0.3 v 0.2 w 0.13 y 0.1 Z (1) 0.72 0.38 8 0o
o
Notes 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. Plastic interlead protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT402-1 REFERENCES IEC JEDEC MO-153 EIAJ EUROPEAN PROJECTION ISSUE DATE 94-07-12 95-04-04
1998 Nov 10
21
Philips Semiconductors
Product specification
Quad bilateral switches
SOLDERING Introduction This text gives a very brief insight to a complex technology. A more in-depth account of soldering ICs can be found in our "Data Handbook IC26; Integrated Circuit Packages" (document order number 9398 652 90011). There is no soldering method that is ideal for all IC packages. Wave soldering is often preferred when through-hole and surface mount components are mixed on one printed-circuit board. However, wave soldering is not always suitable for surface mount ICs, or for printed-circuit boards with high population densities. In these situations reflow soldering is often used. Through-hole mount packages SOLDERING BY DIPPING OR BY SOLDER WAVE The maximum permissible temperature of the solder is 260 C; solder at this temperature must not be in contact with the joints for more than 5 seconds. The total contact time of successive solder waves must not exceed 5 seconds. The device may be mounted up to the seating plane, but the temperature of the plastic body must not exceed the specified maximum storage temperature (Tstg(max)). If the printed-circuit board has been pre-heated, forced cooling may be necessary immediately after soldering to keep the temperature within the permissible limit. MANUAL SOLDERING Apply the soldering iron (24 V or less) to the lead(s) of the package, either below the seating plane or not more than 2 mm above it. If the temperature of the soldering iron bit is less than 300 C it may remain in contact for up to 10 seconds. If the bit temperature is between 300 and 400 C, contact may be up to 5 seconds. Surface mount packages REFLOW SOLDERING Reflow soldering requires solder paste (a suspension of fine solder particles, flux and binding agent) to be applied to the printed-circuit board by screen printing, stencilling or pressure-syringe dispensing before package placement. Several methods exist for reflowing; for example, infrared/convection heating in a conveyor type oven. Throughput times (preheating, soldering and cooling) vary between 100 and 200 seconds depending on heating method. 1998 Nov 10 22 MANUAL SOLDERING
74HC/HCT4066
Typical reflow peak temperatures range from 215 to 250 C. The top-surface temperature of the packages should preferable be kept below 230 C. WAVE SOLDERING Conventional single wave soldering is not recommended for surface mount devices (SMDs) or printed-circuit boards with a high component density, as solder bridging and non-wetting can present major problems. To overcome these problems the double-wave soldering method was specifically developed. If wave soldering is used the following conditions must be observed for optimal results: * Use a double-wave soldering method comprising a turbulent wave with high upward pressure followed by a smooth laminar wave. * For packages with leads on two sides and a pitch (e): - larger than or equal to 1.27 mm, the footprint longitudinal axis is preferred to be parallel to the transport direction of the printed-circuit board; - smaller than 1.27 mm, the footprint longitudinal axis must be parallel to the transport direction of the printed-circuit board. The footprint must incorporate solder thieves at the downstream end. * For packages with leads on four sides, the footprint must be placed at a 45 angle to the transport direction of the printed-circuit board. The footprint must incorporate solder thieves downstream and at the side corners. During placement and before soldering, the package must be fixed with a droplet of adhesive. The adhesive can be applied by screen printing, pin transfer or syringe dispensing. The package can be soldered after the adhesive is cured. Typical dwell time is 4 seconds at 250 C. A mildly-activated flux will eliminate the need for removal of corrosive residues in most applications.
Fix the component by first soldering two diagonally-opposite end leads. Use a low voltage (24 V or less) soldering iron applied to the flat part of the lead. Contact time must be limited to 10 seconds at up to 300 C. When using a dedicated tool, all other leads can be soldered in one operation within 2 to 5 seconds between 270 and 320 C.
Philips Semiconductors
Product specification
Quad bilateral switches
Suitability of IC packages for wave, reflow and dipping soldering methods
74HC/HCT4066
SOLDERING METHOD MOUNTING PACKAGE WAVE Through-hole mount DBS, DIP, HDIP, SDIP, SIL Surface mount HLQFP, HSQFP, HSOP, SMS PLCC(4), SQFP SSOP, TSSOP, VSO Notes 1. All surface mount (SMD) packages are moisture sensitive. Depending upon the moisture content, the maximum temperature (with respect to time) and body size of the package, there is a risk that internal or external package cracks may occur due to vaporization of the moisture in them (the so called popcorn effect). For details, refer to the Drypack information in the "Data Handbook IC26; Integrated Circuit Packages; Section: Packing Methods". 2. For SDIP packages, the longitudinal axis must be parallel to the transport direction of the printed-circuit board. 3. These packages are not suitable for wave soldering as a solder joint between the printed-circuit board and heatsink (at bottom version) can not be achieved, and as solder may stick to the heatsink (on top version). 4. If wave soldering is considered, then the package must be placed at a 45 angle to the solder wave direction. The package footprint must incorporate solder thieves downstream and at the side corners. 5. Wave soldering is only suitable for LQFP, QFP and TQFP packages with a pitch (e) equal to or larger than 0.8 mm; it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.65 mm. 6. Wave soldering is only suitable for SSOP and TSSOP packages with a pitch (e) equal to or larger than 0.65 mm; it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.5 mm. DEFINITIONS Data sheet status Objective specification Preliminary specification Product specification Limiting values Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information Where application information is given, it is advisory and does not form part of the specification. LIFE SUPPORT APPLICATIONS These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such improper use or sale. This data sheet contains target or goal specifications for product development. This data sheet contains preliminary data; supplementary data may be published later. This data sheet contains final product specifications. SO LQFP, QFP, TQFP suitable(2) not suitable(3) suitable not recommended(4)(5) not suitable not recommended(6) REFLOW(1) - suitable suitable suitable suitable suitable - - - - - DIPPING suitable
1998 Nov 10
23
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For all other countries apply to: Philips Semiconductors, International Marketing & Sales Communications, Building BE-p, P.O. Box 218, 5600 MD EINDHOVEN, The Netherlands, Fax. +31 40 27 24825 (c) Philips Electronics N.V. 1998
SCA60
All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights.
Printed in The Netherlands
245106/00/03/pp24
Date of release: 1998 Nov 10
Document order number:
9397 750 04779

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